An integrated circuit (“IC”) experiences different kinds of testing during its production lifecycle. After an IC is manufactured, a high coverage IC test on a dedicated IC tester finds any defects that may have occurred during manufacturing. After assembling the IC to a printed circuit board (“PCB”), an in-circuit board test tests whether the IC was assembled to the PCB properly and whether any damage occurred during the assembly process. Upon return of a PCB from the field, an in-circuit board tester may attempt to identify and locate a faulty part for replacement. Typically, an in-circuit board tester is limited in the speed and memory capacity which it can draw upon to test a single IC on the PCB and the comprehensiveness with which it can test all failure modes for the IC. It is beneficial, therefore, to have a test that may be run at the PCB level, that is reasonably fast, while using limited board tester resources. Conventionally, this kind of test is controlled by the individual IC's that populate the PCB and is conventionally known as an IC's built in self-test (“BIST”).
One type of BIST stimulates the inputs of the IC with a pseudo-random bit sequence and records a reference signature of the IC outputs from an IC known to be operational. The BIST then stimulates the IC to be tested with the same pseudo-random bit sequence and compares the resulting signature with the recorded reference signature. If the resulting signature matches the reference signature, the part is considered functional and passes the BIST. Another type of BIST shifts random patterns into scanpaths on a chip, steps a clock, and then compresses the results into a signature that can be compared to the signature for a known good part.
Certain IC's present a challenge for BIST using pseudo-random bit sequences shifted into registers on the IC. One kind of IC that presents this challenge is an IC comprising one or more memory elements. When using a random number stimulus BIST for an IC with memory elements, patterns that would not occur during normal operation may be shifted into registers. These non-standard register contents can create contention conditions that would not occur during actual operation of the IC. An example of such a contention condition is a stimulus that attempts to read and write to the same location in a memory element. The logic timing of the simultaneous read and write is non-deterministic. Accordingly, a BIST result that included the simultaneous read and write is also non-deterministic, thereby rendering the test unusable for its intended purpose.
Because contention conditions compromise the repeatability of a BIST resulting signature, some prior art solutions test the IC logic first and thereafter test the memory elements with a stimulus that creates only repeatable resulting signatures. This dual mode testing method disadvantageously adds time to the overall test of the IC. Additionally, because this method tests the logic separately from the memory, it may not adequately stimulate the interface logic between the logic and memory sections of the IC and the IC may not receive full test coverage. There is a need, therefore, for an apparatus and method permitting simultaneous BIST testing of the logic and memory elements within an IC.
Some prior art solutions for testing the logic and memory elements simultaneously require additional logic circuitry dedicated to the memory element BIST. The additional logic circuitry represents BIST overhead and takes up space on the IC die. To the extent that logic gates dedicated to BIST testing are inserted in series with other IC logic, this overhead inserts timing delays in the IC's normal operation. This overhead adds to the production costs of the IC and may compromise IC performance, which either increases price or decreases profit. While the BIST overhead for an IC with a large number of relatively small memory elements is greater from a relative perspective than an IC with a few relatively large memory elements, as a general proposition it is universally beneficial to reduce the amount of BIST overhead present on an IC. There is a need, therefore, for an apparatus and method for a reliable IC BIST that permits simultaneous testing of logic and memory elements while adding minimal overhead circuitry and logic timing delays to the IC.